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Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER FEATURES * High speed 4:1 differential multiplexer * One differential LVDS output * Four selectable differential clock inputs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: 2.8GHz * Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input * Part-to-part skew: 375ps (maximum) * Propagation delay: 700ps (maximum) * Supply voltage range: 3.135V to 3.465V * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS compliant packages GENERAL DESCRIPTION The ICS854054 is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.8GHz and HiPerClockSTM is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS854054 has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels. The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits. The select pins have internal pulldown resistors. The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0). IC S BLOCK DIAGRAM PCLK0 nPCLK0 PCLK1 nPCLK1 PCLK2 nPCLK2 PCLK3 nPCLK3 PIN ASSIGNMENT PCLK0 nPCLK0 PCLK1 nPCLK1 VDD SEL0 SEL1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q nQ GND nPCLK3 PCLK3 nPCLK2 PCLK2 00(default) 01 Q nQ 10 ICS854054 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View 11 SEL1 SEL0 854054AG www.icst.com/products/hiperclocks.html 1 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Type Input Input Input Input Power Input Power Input Input Input Input Output Pulldown Pulldown Pulldown Pullup/Pulldown Pulldown Pullup/Pulldown Description Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Positive supply pins. Clock select input pins. LVCMOS/LVTTL interface levels. Power supply ground. Non-inver ting differential clock input. Inver ting differential clock input. Pullup/Pulldown VDD/2 default when left floating. Pulldown Pullup/Pulldown Non-inver ting differential clock input. Inver ting differential clock input. VDD/2 default when left floating. Differential output pair. LVDS interface levels. TABLE 1. PIN DESCRIPTIONS Number 1 2 3 4 5, 16 6, 7 8, 13 9 10 11 12 14, 15 Name PCLK0 nPCLK0 PCLK1 nPCLK1 VDD SEL0, SEL1 GND PCLK2 nPCLK2 PCLK3 nPCLK3 nQ0, Q0 NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol RPULLDOWN RVDD/2 Parameter Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs SEL1 0 0 1 1 SEL0 0 1 0 1 Q PCLK0 PCLK1 PCLK2 PCLK3 Outputs nQ nPCLK0 nPCLK1 nPCLK2 nPCLK3 854054AG www.icst.com/products/hiperclocks.html 2 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER 5.5V -0.5V to VDD + 0.5 V 10mA 15mA 89C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 90 Units V mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, TA = -40C TO 85C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -10 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 Units V V A A TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol Parameter IIH IIL VPP Input High Current Input Low Current PCLK0:PCLK3 nPCLK0:nPCLK3 PCLK0:PCLK3 nPCLK0:nPCLK3 Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -10 -150 0.15 1.2 VDD Minimum Typical Maximum 150 150 Units A A A A V V Peak-to-Peak Input Voltage VCMR Common Mode Input Voltage; NOTE 1, 2 1.2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKx or nPCLKx is VDD + 0.3V. 854054AG www.icst.com/products/hiperclocks.html 3 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER Test Conditions Minimum 250 1.125 Typical 450 1.25 Maximum 525 50 1.375 50 Units mV mV V mV TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change TABLE 5. AC CHARACTERISTICS, VDD = 3.135V TO 3.465V, TA = -40C TO 85C Symbol fMAX tPD t jit t sk(pp) t sk(i) t R / tF Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Par t-to-Par t Skew; NOTE 2, 3 Input Skew Output Rise/Fall Time 325 155.52 MHz, (12kHz - 20MHz) 0.195 375 90 250 Test Conditions Minimum Typical Maximum 2.8 700 Units GHz ps ps ps ps ps dB 20% to 80% 50 155.52MHz, MUXISOLATION MUX Isolation -50 Input Peak-to-Peak = 800mV All parameters measured up to 1.5MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined according with JEDEC Standard 65. 854054AG www.icst.com/products/hiperclocks.html 4 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER ADDITIVE PHASE JITTER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 -20 -30 -40 -50 -60 the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. Additive Phase Jitter, RMS @ 155.52MHz (12kHz - 20MHz) = <0.195ps typical SSB PHASE NOISE dBc/HZ -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 854054AG www.icst.com/products/hiperclocks.html 5 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER PARAMETER MEASUREMENT INFORMATION V DD SCOPE Qx 3.3V5% Power Supply Float GND + - nPCLK0:3 LVDS nQx V PP Cross Points V CMR PCLK0:3 GND 3.3V OUTPUT LOAD AC TEST CIRCUIT nPCLK0:3 PCLK0:3 nQ0 Q0 tPD DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQy PART 2 Qy tsk(pp) PROPAGATION DELAY PART-TO-PART SKEW nPCLK0 PCLK0 80% Clock Outputs 80% VOD nPCLK1 PCLK1 nQ Q tPD2 tPD1 tsk(i) 20% tR tF 20% tsk(i) = |tPD1 - tPD2| OUTPUT RISE/FALL TIME INPUT SKEW VDD VDD out out DC Input DC Input LVDS 100 VOD/ VOD out out VOS/ VOS DIFFERENTIAL OUTPUT VOLTAGE 854054AG OFFSET VOLTAGE www.icst.com/products/hiperclocks.html 6 REV. A MARCH 29, 2006 LVDS Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT PINS INPUTS: PCLK/nPCLK INPUT: For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resister can be tied from PCLK to ground. SELECT PINS: All select pins have internal pull-ups and pull-downs; additional resistance is not required but can be added for additional protection. A 1k resister can be used. 854054AG www.icst.com/products/hiperclocks.html 7 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER gested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and V OH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces sug- 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 60 Ohm 2.5V 2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120 R2 50 Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK nPCLK HiPerClockS PCLK/nPCLK R1 120 R2 120 FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL IN DRIVER 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm CLK nCLK Receiv er FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK R5 100 - 200 R6 100 - 200 R1 125 R2 125 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 854054AG www.icst.com/products/hiperclocks.html 8 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the 3.3V LVDS_Driv er + R1 100 - 100 Ohm Differiential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 854054AG www.icst.com/products/hiperclocks.html 9 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS854054. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854054 is the sum of the core power. The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature qJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 81.8C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.312W * 81.8C/W = 110.5C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 16-LEAD TSSOP, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W 200 118.2C/W 81.8C/W 500 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 854054AG www.icst.com/products/hiperclocks.html 10 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1C/W 89.0C/W 200 118.2C/W 81.8C/W 500 106.8C/W 78.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS854054 is: 361 854054AG www.icst.com/products/hiperclocks.html 11 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER 16 LEAD TSSOP PACKAGE OUTLINE - G SUFFIX FOR TABLE 8. PACKAGE DIMENSIONS SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 8 0.10 Millimeters Minimum 16 1.20 0.15 1.05 0.30 0.20 5.10 Maximum Reference Document: JEDEC Publication 95, MO-153 854054AG www.icst.com/products/hiperclocks.html 12 REV. A MARCH 29, 2006 Integrated Circuit Systems, Inc. ICS854054 4:1 DIFFERENTIAL-TO-LVDS CLOCK MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS854054AG 854054AG 16 Lead TSSOP tube -40C to 85C ICS854054AGT 854054AG 16 Lead TSSOP 2500 tape & reel -40C to 85C ICS854054AGLF TBD 16 Lead TSSOP tube -40C to 85C ICS854054AGLFT TBD 16 Lead TSSOP 2500 tape & reel -40C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854054AG www.icst.com/products/hiperclocks.html 13 REV. A MARCH 29, 2006 |
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